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1 features ? fast read access time ? 70 ns 5-volt only reprogramming sector program operation ? single cycle reprogram (erase and program) ? 512 sectors (128 bytes/sector) ? internal address and data latches for 128 bytes internal program control and timer hardware and software data protection fastsectorprogramcycletime?10ms data polling for end of program detection low power dissipation ? 50maactivecurrent ?100 a cmos standby current typical endurance > 10,000 cycles single 5v 10% supply cmos and ttl compatible inputs and outputs commercial and industrial temperature ranges description the AT29C512 is a 5-volt only in-system flash programmable and erasable read only memory (perom). its 512k of memory is organized as 65,536 words by 8 bits. man- ufactured with atmel?s advanced nonvolatile cmos technology, the device offers access times to 70 ns with power dissipation of just 275 mw over the commercial tem- perature range. when the device is deselected, the cmos standby current is less than 100 a. the device endurance is such that any sector can typically be written to in excess of 10,000 times. 512k (64k x 8) 5-volt only flash memory AT29C512 rev. 0456f?flash?12/02 pin configurations pin name function a0 - a15 addresses ce chip enable oe output enable we write enable i/o0 - i / o7 data inputs/outputs nc no connect tsop top view type 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a11 a9 a8 a13 a14 nc we vcc nc nc a15 a12 a7 a6 a5 a4 oe a10 ce i/o7 i/o6 i/o5 i/o4 i/o3 gnd i/o2 i/o1 i/o0 a0 a1 a2 a3 dip top view plcc top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 nc nc a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 gnd vcc we nc a14 a13 a8 a9 a11 oe a10 ce i/o7 i/o6 i/o5 i/o4 i/o3 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 a14 a13 a8 a9 a11 oe a10 ce i/o7 4 3 2 1 32 31 30 14 15 16 17 18 19 20 i/o1 i/o2 gnd i/o3 i/o4 i/o5 i/o6 a12 a15 nc nc vcc we nc
2 AT29C512 0456f?flash?12/02 to allow for simple in-system reprogrammability, the AT29C512 does not require high input voltages for programming. five-volt-only commands determine the operation of the device. reading data out of the device is similar to reading from an eprom. reprogramming the AT29C512 is performed on a sector basis; 128 bytes of data are loaded into the device and then simultaneously programmed. during a reprogram cycle, the address locations and 128 bytes of data are internally latched, freeing the address and data bus for other operations. following the initiation of a program cycle, the device will automatically erase the sector and then program the latched data using an internal control timer. the end of a program cycle can be detected by data polling of i/o7. once the end of a program cycle has been detected, a new access for a read or program can begin. block diagram device operation read: theAT29C512isaccessedlikeaneprom.whence and oe are low and we is high, the data stored at the memory location determined by the address pins is asserted on the outputs. the outputs are put in the high impedance state whenever ce or oe is high. this dual-line control gives designers flexibility in preventing bus contention. byte load: byte loads are used to enter the 128 bytes of a sector to be programmed or the software codes for data protection. a byte load is performed by applying a low pulse on the we or ce input with ce or we low (respectively) and oe high. the address is latched on the falling edge of ce or we , whichever occurs last. the data is latched by the first rising edge of ce or we . program: the device is reprogrammed on a sector basis. if a byte of data within a sector is to be changed, data for the entire sector must be loaded into the device. any byte that is not loaded during the programming of its sector will be indeterminate. once the bytes of a sector are loaded into the device, they are simultaneously programmed during the internal program- ming period. after the first data byte has been loaded into the device, successive bytes are entered in the same manner. each new byte to be programmed must have its high-to-low tran- sition on we (or ce ) within 150 s of the low-to-high transition of we (or ce ) of the preceding byte. if a high-to-low transition is not detected within 150 s of the last low-to-high transition, the load period will end and the internal programming period will start. a7 to a15 specify the sector address. the sector address must be valid during each high-to-low transition of we (or ce ). a0 to a6 specify the byte address within the sector. the bytes may be loaded in any order; sequential loading is not required. once a programming operation has been initiated, and for the duration of t wc , a read operation will effectively be a polling operation.
3 AT29C512 0456f?flash?12/02 software data protection: a software controlled data protection feature is avail- able on the AT29C512. once the software protection is enabled a software algorithm must be issued to the device before a program may be performed. the software protection feature may be enabled or disabled by the user; when shipped from atmel, the software data protection feature is disabled. to enable the software data protection, a series of three program com- mands to specific addresses with specific data must be performed. after the software data protection is enabled the same three program commands must begin each program cycle in order for the programs to occur. all software program commands must obey the sector pro- gram timing specifications. once set, the software data protection feature remains active unless its disable command is issued. power transitions will not reset the software data pro- tection feature; however, the software feature will guard against inadvertent program cycles during power transitions. once set, software data protection will remain active unless the disable command sequence is issued. after setting sdp, any attempt to write to the device without the 3-byte command sequence will start the internal write timers. no data will be written to the device; however, for the dura- tion of t wc , a read operation will effectively be a polling operation. after the software data protection?s 3-byte command code is given, a byte load is performed by applying a low pulse on the we or ce input with ce or we low (respectively) and oe high. the address is latched on the falling edge of ce or we , whichever occurs last. the data is latched by the first rising edge of ce or we . the 128 bytes of data must be loaded into each sector by the same procedure as outlined in the program section under device operation. hardware data protection: hardware features protect against inadvertent pro- grams to the AT29C512 in the following ways: (a) v cc sense ? if v cc is below 3.8v (typical), the program function is inhibited; (b) v cc power on delay ? once v cc has reached the v cc sense level, the device will automatically time out 5 ms (typical) before programming; (c) pro- gram inhibit ? holding any one of oe low, ce high or we high inhibits program cycles; and (d) noise filter ? pulses of less than 15 ns (typical) on the we or ce inputs will not initiate a pro- gram cycle. product identification: the product identification mode identifies the device and manufacturer as atmel. it may be accessed by hardware or software operation. the hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the atmel product. in addition, users may wish to use the software product identi- fication mode to identify the part (i.e., using the device code), and have the system software use the appropriate sector size for program operations. in this manner, the user can have a common board design for 256k to 4-megabit densities and, with each density?s sector size in a memory map, have the system software apply the appropriate sector size. for details, see operating modes (for hardware operation) or software product identification. the manufacturer and device code is the same for both modes.
4 AT29C512 0456f?flash?12/02 data polling: the AT29C512 features data polling to indicate the end of a program cycle. during a program cycle an attempted read of the last byte loaded will result in the com- plement of the loaded data on i/o7. once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. data polling may begin at any time during the program cycle. toggle bit: in addition to data polling the AT29C512 provides another method for deter- mining the end of a program or erase cycle. during a program or erase operation, successive attempts to read data from the device will result in i/o6 toggling between one and zero. once the program cycle has completed, i/o6 will stop toggling and valid data will be read. examin- ing the toggle bit may begin at any time during a program cycle. optional chip erase mode: the entire device can be erased by using a 6-byte soft- ware code. please see software chip erase application note for details. absolute maximum ratings* temperature under bias ................................ -55 cto+125 c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature ..................................... -65 cto+150 c all input voltages (including nc pins) with respect to ground ...................................-0.6v to +6.25v all output voltages with respect to ground .............................-0.6v to v cc +0.6v voltage on oe with respect to ground ...................................-0.6v to +13.5v
5 AT29C512 0456f?flash?12/02 notes: 1. x can be v il or v ih . 2. refer to ac programming waveforms. 3. v h = 12.0v 0.5v. 4. manufacturer code: 1f, device code: 5d. 5. see details under software product identification entry/exit. dc and ac operating range AT29C512-70 AT29C512-90 AT29C512-12 AT29C512-15 operating temperature (case) com. 0 c-70 c0 c-70 c 0 c-70 c 0 c-70 c ind. -40 c-85 c-40 c-85 c -40 c-85 c -40 c-85 c v cc power supply 5v 5% 5v 10% 5v 10% 5v 10% note: not recommended for new designs. operating modes mode ce oe we ai i/o read v il v il v ih ai d out program (2) v il v ih v il ai d in 5v chip erase v il v ih v il ai standby/write inhibit v ih x (1) xxhighz program inhibit x x v ih program inhibit x v il x output disable x v ih xhighz product identification hardware v il v il v ih a1 - a15 = v il ,a9=v h , (3) a0 = v il manufacturer code (4) a1-a15 = v il ,a9=v h , (3) a0 = v ih device code (4) software (5) a0 = v il manufacturer code (4) a0 = v ih device code (4) dc characteristics symbol parameter condition min max units i li input load current v in =0vtov cc 10 a i lo output leakage current v i/o =0vtov cc 10 a i sb1 v cc standby current cmos ce =v cc -0.3vtov cc com. 100 a ind. 300 a i sb2 v cc standby current ttl ce =2.0vtov cc 3ma i cc v cc active current f = 5 mhz; i out = 0 ma 50 ma v il input low voltage 0.8 v v ih input high voltage 2.0 v v ol output low voltage i ol =2.1ma 0.45 v v oh1 output high voltage i oh =-400 a2.4v v oh2 output high voltage cmos i oh =-100 a; v cc =4.5v 4.2 v
6 AT29C512 0456f?flash?12/02 ac read waveforms (1)(2)(3)(4) notes: 1. ce may be delayed up to t acc -t ce after the address transition without impact on t acc . 2. oe may be delayed up to t ce -t oe after the falling edge of ce without impact on t ce or by t acc -t oe after an address change without impact on t acc . 3. t df is specified from oe or ce whichever occurs first (cl = 5 pf). 4. this parameter is characterized and is not 100% tested. ac read characteristics symbol parameter AT29C512-70 AT29C512-90 AT29C512-12 AT29C512-15 units min max min max min max min max t acc address to output delay 70 90 120 150 ns t ce (1) ce to output delay 70 90 120 150 ns t oe (2) oe to output delay 0 35 0 40 0 50 0 70 ns t df (3)(4) ce or oe to output float 0 10 0 25 0 30 0 40 ns t oh output hold from oe ,ce or address, whichever occurred first 00 0 0 ns note: not recommended for new designs.
7 AT29C512 0456f?flash?12/02 input test waveforms and measurement level output test load note: 1. this parameter is characterized and is not 100% tested. t r ,t f <5ns output pin 5.0v 30pf 1.8k 1.3k output pin 5.0v 100pf 1.8k 1.3k 70 ns 90/120/150 ns pin capacitance f=1mhz,t=25c (1) symbol typ max units conditions c in 46pfv in =0v c out 812pfv out =0v
8 AT29C512 0456f?flash?12/02 ac byte load waveforms we controlled ce controlled ac byte load characteristics symbol parameter min max units t as ,t oes address, oe set-up time 0 ns t ah address hold time 50 ns t cs chip select set-up time 0 ns t ch chip select hold time 0 ns t wp write pulse width (we or ce )90ns t ds data set-up time 35 ns t dh ,t oeh data, oe hold time 0 ns t wph write pulse width high 100 ns t dh t ds t as t ah t wp ce address data in oe t oes t oeh we t cs t ch t wph t dh t ds t as t ah t wp we address data in oe t oes t oeh ce t cs t ch t wph
9 AT29C512 0456f?flash?12/02 program cycle waveforms (1)(2)(3) notes: 1. a7 through a15 must specify the sector address during each high-to-low transition of we (or ce ). 2. oe must be high when we and ce arebothlow. 3. all bytes that are not loaded within the sector being programmed will be indeterminate. program cycle characteristics symbol parameter min max units t wc writecycletime 10 ms t as address set-up time 0 ns t ah address hold time 50 ns t ds data set-up time 35 ns t dh data hold time 0 ns t wp write pulse width 90 ns t blc byte load cycle time 150 s t wph write pulse width high 100 ns
10 AT29C512 0456f?flash?12/02 software data protection enable algorithm (1) notes: 1. data format: i/o7 - i/o0 (hex);address format: a14 - a0 (hex). 2. data protect state will be activated at end of program cycle. 3. data protect state will be deactivated at end of pro- gram period. 4. 128 bytes of data must be loaded. load data aa to address 5555 load data 55 to address 2aaa load data a0 to address 5555 load data to page (128 bytes) (4) writes enabled enter data protect state (2) software data protection disable algorithm (1) load data aa to address 5555 load data 55 to address 2aaa load data 80 to address 5555 load data aa to address 5555 load data 55 to address 2aaa load data 20 to address 5555 load data to page (128 bytes) (4) exit data protect state (3) software protected program cycle waveform (1)(2)(3) notes: 1. a7 through a15 must specify the page address during each high-to-low transition of we (or ce ) after the software code has been entered. 2. oe must be high when we and ce arebothlow. 3. all bytes that are not loaded within the sector being programmed will be indeterminate. oe (1) ce we data (3) byte 0 byte 126 byte 127 t dh t blc t ds t wp t wph t ah a0-a6 a7-a15 (2) t wc 5555 2aaa 5555 aa 55 a0 t as sector address byte address
11 AT29C512 0456f?flash?12/02 notes: 1. these parameters are characterized and not 100% tested. 2. see t oe spec in ac read characteristics. data polling waveforms notes: 1. these parameters are characterized and not 100% tested. 2. see t oe spec in ac read characteristics. toggle bit waveforms (1)(2)(3) notes: 1. toggling either oe or ce or both oe and ce will operate toggle bit. 2. beginning and ending state of i/o6 will vary. 3. any address location may be used but the address should not vary. data polling characteristics (1) symbol parameter min typ max units t dh data hold time 10 ns t oeh oe hold time 10 ns t oe oe to output delay (2) ns t wr write recovery time 0 ns toggle bit characteristics (1) symbol parameter min typ max units t dh data hold time 10 ns t oeh oe hold time 10 ns t oe oe to output delay (2) ns t oehp oe high pulse 150 ns t wr write recovery time 0 ns we ce oe i/o6 (2) t oeh high z t dh t oe t wr
12 AT29C512 0456f?flash?12/02 software product identification entry (1) load data aa to address 5555 load data 55 to address 2aaa load data 90 to address 5555 pause 10 ms enter product identification mode (2)(3)(5) software product identification exit (1) load data aa to address 5555 load data 55 to address 2aaa load data f0 to address 5555 pause 10 ms exit product identification mode (4) notes: 1. data format: i/o7 - i/o0 (hex); address format: a14 - a0 (hex). 2. a1 - a15 = v il . manufacturer code is read for a0 = v il ;devicecodeisreadfora0=v ih . 3. the device does not remain in identification mode if powered down. 4. the device returns to standard operation mode. 5. manufacturer code is 1f. the device code is 5d.
13 AT29C512 0456f?flash?12/02 normalized supply current vs. temperature temperature (c) -55 1.4 1.3 1.2 1.1 1.0 0.8 0.9 -25 5 35 65 95 125 n o r m a l i z e d i c c normalized supply current vs. address frequency frequency (mhz) 0 1.1 1.0 0.9 0.8 0.7 1234567 n o r m a l i z e d i c c v cc = 5v t = 25c normalized supply current vs. supply voltage supply voltage (v) 4.50 1.4 1.2 1.0 0.8 0.6 4.75 5.00 5.25 5.50 n o r m a l i z e d i c c
14 AT29C512 0456f ? flash ? 12/02 ordering information t acc (ns) i cc (ma) ordering code package operation range active standby 70 50 0.1 AT29C512-70jc AT29C512-70pc AT29C512-70tc 32j 32p6 32t commercial (0 to 70 c) 50 0.1 AT29C512-70ji AT29C512-70ti 32j 32t industrial (-40 to 85 c) 90 50 0.1 AT29C512-90jc AT29C512-90pc AT29C512-90tc 32j 32p6 32t commercial (0 to 70 c) 50 0.3 AT29C512-90ji AT29C512-90pi AT29C512-90ti 32j 32p6 32t industrial (-40 to 85 c) 120 50 0.1 AT29C512-12jc AT29C512-12pc AT29C512-12tc 32j 32p6 32t commercial (0 to 70 c) 50 0.3 AT29C512-12ji AT29C512-12pi AT29C512-12ti 32j 32p6 32t industrial (-40 to 85 c) 150 50 0.1 AT29C512-15jc AT29C512-15pc AT29C512-15tc 32j 32p6 32t commercial (0 to 70 c) 50 0.3 AT29C512-15ji AT29C512-15pi AT29C512-15ti 32j 32p6 32t industrial (-40 to 85 c) note: not recommended for new designs. package type 32j 32-lead, plastic j-leaded chip carrier (plcc) 32p6 32-pin, 0.600" wide, plastic dual inline package (pdip) 32t 32-lead, thin small outline package (tsop)
15 AT29C512 0456f ? flash ? 12/02 packaging information 32j ? plcc drawing no. rev. 2325 orchard parkway san jose, ca 95131 r title 32j , 32-lead, plastic j-leaded chip carrier (plcc) b 32j 10/04/01 1.14(0.045) x 45? pin no. 1 identifier 1.14(0.045) x 45? 0.51(0.020)max 0.318(0.0125) 0.191(0.0075) a2 45? max (3x) a a1 b1 e2 b e e1 e d1 d d2 common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this package conforms to jedec reference ms-016, variation ae. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is .010"(0.254 mm) per side. dimension d1 and e1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. lead coplanarity is 0.004" (0.102 mm) maximum. a 3.175 3.556 a1 1.524 2.413 a2 0.381 d 12.319 12.573 d1 11.354 11.506 note 2 d2 9.906 10.922 e 14.859 15.113 e1 13.894 14.046 note 2 e2 12.471 13.487 b 0.660 0.813 b1 0.330 0.533 e 1.270 typ
16 AT29C512 0456f ? flash ? 12/02 32p6 ? pdip 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 32p6 , 32-lead (0.600"/15.24 mm wide) plastic dual inline package (pdip) b 32p6 09/28/01 pin 1 e1 a1 b ref e b1 c l seating plane a 0 ~ 15 d e eb common dimensions (unit of measure = mm) symbol min nom max note a 4.826 a1 0.381 d 41.783 42.291 note 1 e 15.240 15.875 e1 13.462 13.970 note 1 b 0.356 0.559 b1 1.041 1.651 l 3.048 3.556 c 0.203 0.381 eb 15.494 17.526 e 2.540 typ note: 1. dimensions d and e1 do not include mold flash or protrusion. mold flash or protrusion shall not exceed 0.25 mm (0.010").
17 AT29C512 0456f ? flash ? 12/02 32t ? tsop 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 32t , 32-lead (8 x 20 mm package) plastic thin small outline package, type i (tsop) b 32t 10/18/01 pin 1 d1 d pin 1 identifier b e e a a1 a2 0 ~ 8 c l gage plane seating plane l1 common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this package conforms to jedec reference mo-142, variation bd. 2. dimensions d1 and e do not include mold protrusion. allowable protrusion on e is 0.15 mm per side and on d1 is 0.25 mm per side. 3. lead coplanarity is 0.10 mm maximum. a 1.20 a1 0.05 0.15 a2 0.95 1.00 1.05 d 19.80 20.00 20.20 d1 18.30 18.40 18.50 note 2 e 7.90 8.00 8.10 note 2 l 0.50 0.60 0.70 l1 0.25 basic b 0.17 0.22 0.27 c 0.10 0.21 e 0.50 basic
printed on recycled paper. 0456f ? flash ? 12/02 /xm ? atmel corporation 2002. atmel corporation makes no warranty for the use of its products, other than those expressly contained in the company ? s standard warranty whichisdetailedinatmel ? s terms and conditions located on the company ? s web site. the company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. no licenses to patents or other intellectual property of atmel are granted by the company in connection with the sale of atmel products, expressly or by implication. atmel ? s products are not authorized for use as critical components in life support devices or systems. atmel headquarters atmel operations corporate headquarters 2325 orchard parkway san jose, ca 95131 tel 1(408) 441-0311 fax 1(408) 487-2600 europe atmel sarl route des arsenaux 41 case postale 80 ch-1705 fribourg switzerland tel (41) 26-426-5555 fax (41) 26-426-5500 asia room 1219 chinachem golden plaza 77 mody road tsimshatsui east kowloon hong kong tel (852) 2721-9778 fax (852) 2722-1369 japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel (81) 3-3523-3551 fax (81) 3-3523-7581 memory 2325 orchard parkway san jose, ca 95131 tel 1(408) 441-0311 fax 1(408) 436-4314 microcontrollers 2325 orchard parkway san jose, ca 95131 tel 1(408) 441-0311 fax 1(408) 436-4314 la chantrerie bp 70602 44306 nantes cedex 3, france tel (33) 2-40-18-18-18 fax (33) 2-40-18-19-60 asic/assp/smart cards zone industrielle 13106 rousset cedex, france tel (33) 4-42-53-60-00 fax (33) 4-42-53-60-01 1150 east cheyenne mtn. blvd. colorado springs, co 80906 tel 1(719) 576-3300 fax 1(719) 540-1759 scottish enterprise technology park maxwell building east kilbride g75 0qr, scotland tel (44) 1355-803-000 fax (44) 1355-242-743 rf/automotive theresienstrasse 2 postfach 3535 74025 heilbronn, germany tel (49) 71-31-67-0 fax (49) 71-31-67-2340 1150 east cheyenne mtn. blvd. colorado springs, co 80906 tel 1(719) 576-3300 fax 1(719) 540-1759 biometrics/imaging/hi-rel mpu/ high speed converters/rf datacom avenue de rochepleine bp 123 38521 saint-egreve cedex, france tel (33) 4-76-58-30-00 fax (33) 4-76-58-34-80 e-mail literature@atmel.com web site http://www.atmel.com at m e l ? is the registered trademark of atmel. other terms and product names may be the trademarks of others.

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